There are image forming devices, such as electrographic printers, in which an exposure part is configured from a plurality of light emitting thyristors arrayed as light emitting elements. In such image forming devices using the light emitting thyristors, a driving circuit and the light emitting thyristors are provided at a ratio of 1:N (N>1). Positions of the light emitting thyristors to be driven are designated by using the gates of the light emitting thyristors. Light emission power is controlled by a value of current that flows between the anode and cathode of the respective light emitting thyristors.
So-called self scanning optical print heads are known as optical print heads that use the light emitting thyristors. When driving a conventional self scanning optical print head under a power source voltage of 3.3 V, gate trigger current cannot be generated with the 3.3 V for the power source voltage. To compensate for this, a configuration is known in which an undershoot voltage is generated in a transfer clock signal waveform (hereinafter “clock signal” is simply referred to as “clock”), and in which the gate trigger current is generated with an added value of the undershoot voltage and 3.3 V for the power source voltage.
For example, according to the technique disclosed in Japanese Laid-Open Patent Application Publication No. 2004-195796, in order to generate the transfer clock waveform, a first output terminal and a second output terminal are provided in a clock driving circuit. A signal from the first output terminal is transmitted to a capacitor-resistor (CR) differential circuit to generate an undershoot waveform, and a direct current component is transmitted through the second output terminal. The reason for the two output terminals per transfer clock in the clock driving circuit is that the direct current component cannot be transmitted through the CR differential circuit.
However, in the conventional self scanning optical print head, there are the following concerns with two output terminals per transfer clock in the clock driving circuit.
In the optical print head, a large number of self scanning light emitting thyristor array chips is provided, and the operation of the self scanning light emitting thyristor array chips is simultaneously performed in parallel for high speed operation. A 2-phase clock is used as a data transfer clock for the light emitting thyristor array chips, and two clocks are inputted to each light emitting thyristor array chip. Therefore, four output terminals are required in a clock driving circuit for the self scanning optical print head for driving each light emitting thyristor array chip.
Because a large number of self scanning light emitting thyristor array chips are arranged in an optical print head, the total number of output terminals provided in a clock driving circuit becomes enormous. If the number of terminals are controlled so that the terminals can be accommodated in a large-scale integration (hereinafter “LSI”) package, a large number of chips that are connected in parallel to and that are driven by a clock driving circuit is required, causing waveform rounding. As a result, there is a problem that the operation of the optical print head cannot be performed at high speed.
A similar problem occurs in a self scanning optical print head that uses a light emitting diode (hereinafter “LED”) as the light emitting element.
Therefore, circuitry is desired that generates clocks for self scanning light emitting element array chips without increasing in the number of terminals that can be accommodated in an LST package that drives the optical print heads.